1. Field of the Invention
The invention relates in general to a liquid crystal display, and more particularly to a disposed structure of a scan line.
2. Description of the Related Art
FIG. 1 is a schematic illustration showing a pixel circuit. Referring to FIG. 1, a pixel 100 includes a thin film transistor TFT, a liquid crystal capacitor CL and a storage capacitor CS. The thin film transistor TFT has a gate G coupled with a scan line SL, a source S coupled with a data line DL, and a drain D coupled with the liquid crystal capacitor CL and the storage capacitor CS. The liquid crystal capacitor CL and the storage capacitor CS store charges for driving liquid crystal molecules.
FIG. 2 is a schematic illustration showing the structure of a conventional liquid crystal display. Referring to FIG. 2, a liquid crystal display 102 includes a scan driver circuit 104, a data driver circuit 106 and a pixel array 108 composed of a plurality of pixels 100. When the liquid crystal display 102 displays frames, the scan driver circuit 104 sequentially outputs N scan signals SS to the corresponding scan line SL so as to turn on the transistors TFT in each row of pixels of the pixel array 108, and the data driver circuit 106 sequentially inputs corresponding pixel voltages VP from the corresponding data lines DL(1) to DL(M) to each row of pixels 100, wherein N and M are positive integers. The pulse waveform of the scan signal SS approximates a square wave and has a voltage level for turning on the transistor TFT.
Because each pixel 100 has the capacitors CL and CS and a capacitor effect exists between the scan line SL and other plates, each scan line SL may be regarded as having the resistor-capacitor (RC) effect. Thus, after the scan signal SS passes through a row of pixels, the square wave of the scan signal SS may have distortion, which is the so-called gate-delay, due to the RC effect in the circuit.
Taking the first row R(1) of pixels as an example, the scan signal SS is inputted to the first row R(1) of pixels through the scan line SL(1), i.e., inputted to the first pixel 100 from the node L of FIG. 2. The scan signal SS is gradually distorted with the increase of the transmission distance on the scan line SL(1). When the signal reaches the rightmost end (i.e., node R of FIG. 2) of the first row R(1) of pixels, the generated distortion is most serious. Because the distorted scan signal SS shortens the time period during which the TFT of the pixel 100 turns on, the time periods during which the pixels at the rightmost and leftmost pixels 100 are different, and the corresponding liquid crystal capacitor CL and the storage capacitor CS have insufficient time periods to store the predetermined charges, such that the predetermined luminance cannot be generated.
Thus, when the same pixel data is to be displayed on the whole frame, the pixels receive the same pixel voltage VP but the luminance at the right-hand side and the luminance at the left-hand side of the frame are not the same. For example, the pixel closest to the node to which the scan signal SS is inputted is the brightest, and the pixel farthest from the node to which the scan signal SS is inputted is the darkest. Thus, the luminance of the overall frame looks very nonuniform, and the image quality is influenced.